RISC-V in Safety-Critical Embedded Systems: Hardware/Software Co-Design and Assurance Cases

Abstract

This review investigates how RISC-V, an open and extensible instruction set architecture, can be effectively adopted in safety-critical embedded systems through integrated hardware/software co-design strategies and structured assurance cases that ensure compliance with functional safety standards. A qualitative systematic review design was employed to synthesize the state of research on RISC-V implementation within safety-critical environments. Seventeen peer-reviewed journal articles and conference papers published between 2015 and 2025 were selected from IEEE Xplore, Scopus, Web of Science, and ACM Digital Library databases based on inclusion criteria emphasizing RISC-V architectures, safety assurance, and verification frameworks. Data collection consisted exclusively of literature review. Thematic analysis using NVivo 14 software was conducted through open, axial, and selective coding, with theoretical saturation achieved at the seventeenth article. Four core themes were extracted: (1) hardware/software co-design paradigms, (2) safety assurance and certification frameworks, (3) open-source ecosystem and verification governance, and (4) energy–latency trade-offs and performance assurance. Results reveal that modular co-design approaches in RISC-V enable domain-specific optimizations while maintaining deterministic timing and verifiability. Structured assurance cases—built on Goal Structuring Notation (GSN) and model-based verification—are emerging as credible mechanisms for aligning open-hardware transparency with certification expectations such as ISO 26262, DO-254, and IEC 61508. The open-source RISC-V ecosystem enhances reproducibility, community validation, and toolchain verification but introduces challenges in provenance tracking and standardization. Furthermore, energy-aware design techniques like dynamic voltage and frequency scaling (DVFS) can improve efficiency without compromising real-time safety guarantees when combined with rigorous timing validation. Collectively, the findings highlight a co-evolution of technical innovation and assurance methodology that redefines safety in open architectures. RISC-V’s adoption in safety-critical domains depends on unifying co-design practices with auditable assurance frameworks that demonstrate both functional safety and transparency. Future progress will hinge on standardized open-hardware certification models, formal verification integration, and collaborative governance to balance innovation with accountability.